Research on hardware and systems for machine learning workloads. Follow findings on throughput, energy use, memory, and deployment constraints.
34 papers · Latest edition October 7, 2026
Three of the latest briefs in this collection. Read the evidence and the original papers alongside them.
An LLM learns to replace parts of the GPU compiler stack by translating Triton code directly into fast, verified PTX kernels.
Purlin makes GPU collective communication more modular and faster, improving large-scale LLM and diffusion inference across modern hardware.
RESOLVE makes AI-written GPU kernels safer by combining race-finding tests with formal proofs that optimized code still computes the right result.
Newest editions first.
François Costa, Charly Castes, Thomas Bourgeat, Azalia Mirhoseini
An LLM learns to replace parts of the GPU compiler stack by translating Triton code directly into fast, verified PTX kernels.
Osayamen Jonathan Aimuyo, Swapnil Gandhi, Christos Kozyrakis
Purlin makes GPU collective communication more modular and faster, improving large-scale LLM and diffusion inference across modern hardware.
Ashkan Vedadi Gargary, Guido Martínez, Sebastian Burckhardt, Gabriel Ebner, Abhinav Jangda, Madan Musuvathi, Tyler Sorensen
RESOLVE makes AI-written GPU kernels safer by combining race-finding tests with formal proofs that optimized code still computes the right result.
Zhengyi Han, Yuanchen Zhao, Yijia Xu, Yixu Wang, Zi-Wen Liu
This work shows that quantum LDPC codes can still reliably correct coherent errors below a universal noise threshold, strengthening the foundations of scalable fault-tolerant quantum computers.
Chris S. Lin, Joyce Qu, Aditya Rajeev, Gururaj Saileshwar
GPUThor shows that carefully timed, non-uniform memory access patterns can turn ECC-protected NVIDIA GPUs into practical targets for powerful Rowhammer attacks.
Haoran Yan, Ziyu Shao, Shuhao Zhang, Qinhong Jiang, Yan Long
The work shows that attackers can inject electromagnetic signals to make hidden audio and sensor data leak from ordinary electronic hardware.
Nathaniel Selub, Aditya Bhardwaj, Ethan Lake
This work proposes a fully local quantum-computing architecture whose continuously operating decoder could make fault-tolerant computation possible in a realistic two-dimensional setting.
Jungmin Park, Eunha Kim, Wooseop Kim, Seongjoon Cho, Byungho Cha
An AI agent designed a post-quantum crypto chip, and rigorous randomized testing exposed and fixed a hardware verification gap that standard tests missed.
Robert Hu
This work redesigns FlashAttention for Blackwell’s FP4 hardware, achieving faster inference and training while showing that aggressively quantized distributed training can become unstable.
Shangkun Wang, Nina Cai, Charles Hoong, Julian Walker, Gerson Kroiz, George Vanica, Deepak Patil, Andi Gavrilescu, Hassan Sipra, Sethu Sankaran
MaxKernel uses collaborating AI agents and compiler feedback to automatically discover high-performance TPU kernels that can rival expert optimization.
Jason Hickey
One researcher uses AI agents and machine-checked verification to move from software ideas to a taped-out RISC-V chip without writing RTL by hand.
Stephan Roschinski, Johannes Schabbauer, Franz von Silva-Tarouca, Marvin Holten, Damien Bloch, Julian Léonard
Researchers combine individually controlled rubidium atoms with a fiber cavity to build a programmable platform for quantum networks and many-body quantum optics.
Architect Labs
Redwood is an AI-designed accelerator that claims to go from specification to verified silicon-ready hardware and efficient model execution in just two weeks.
Zeyu Cao, Xuan Guo, Cheng Zhang, Cheuk Hang Lau, Ilia Shumailov, Yiren Zhao
A 128-GPU cluster assembled from discarded hardware can serve LLaMA-70B cheaply, but its environmental value depends heavily on electricity costs and carbon intensity.
Ishaan Kannan, Sridhar Prabhu, Saeed A. Khan, Mandar M. Sohoni, Xingrui Song, Saswata Roy, Alen Senanian, Valla Fatemi, Peter L. McMahon, Jordan Cotler
A single controllable qubit dramatically cuts the measurements needed to learn classical signals, suggesting powerful near-term applications for quantum-enhanced sensing.
Xiangfeng Sun, Ceyu Xu, Ningzhi Ai, Zeyu Zhu, Yiyang Yuan, Yuan Xie
Agents iteratively diagnose prefetching failures and synthesize specialized hardware components that reportedly outperform leading human-designed prefetchers.
Willers Yang, Casey Duckering, Arpit Dua
GALA designs compact quantum error-correcting codes that are built from the outset to fit the movement constraints and operations of neutral-atom quantum hardware.
Tianhong Xu, Saion K. Roy, Ruyi Ding, Aidong Adam Ding, Yunsi Fei
Researchers show that an unprivileged CPU process can spy on GPU workloads running on Apple Silicon by tracking footprints in the shared cache.
Fariba Islam, Chang-Min Lee, Kyu-Young Kim, Sorah Fischer, Purbita Purkayastha, Edo Waks
A thin Al2O3 coating makes silicon T-center photons more spectrally stable, bringing indistinguishable telecom quantum emitters closer to practical devices.
Ziyi Yang, Wenji Fang, Chen Chen, Zhiyao Xie, Hongce Zhang
CircuitProver uses an AI agent and reusable Lean proof libraries to make formal hardware verification faster and more transferable across related circuit designs.
Conor James Green, William Won, Tuan Ta, Bradford M. Beckmann
NUNA speeds up multi-GPU inference by routing communication and placing computation with awareness of where traffic travels inside large GPU systems.
Eylon E. Krause
Shiftfly replaces a costly all-to-all optical tier with a compact shift-routed topology that scales accelerator clusters to hundreds of thousands of chips, while exposing tradeoffs in locality and slice allocation.
Bowen Wang, Chi Zhang, Diyou Shen, Renzo Andri, Navaneeth Kunhi Purayil, Luca Benini
Ventaglio is a compact vector-processor hardware extension that makes sparse Transformer inference substantially faster by accelerating the indexed memory operations that conventional architectures handle inefficiently.
Yitong Ding, Jiawei Huang, Renyang Guan, Yangjie Zhou, Zihan Liu, Yu Feng, Shixuan Sun, Mingyi Guo, Jingwen Leng, Jian Weng
GPU-Tile-Sim models LLM GPU performance through dependency-aware tile graphs, offering a faster and more adaptable tool for hardware-software co-design.
Stefan Scholze, Johannes Partzsch, Sebastian Höppner, Florian Kelber, Andreas Dixius, Marco Stolba, Sirine Arfa, Marc Berthel, Georg Ellguth, Jim Garside, Hector A. Gonzalez, Stephan Hartmann, Thomas Kiel-Hocker, Dongwei Hu, Matthias Jobst, Khaleelulla Khan Nazeer, Tim Langer, Chen Liu, Gengting Liu, Matthias Lohrmann, Mantas Mikaitis, Felix Neumärker, Amirhossein Rostami, Stefan Schiefer, Tilo Schubert, Delong Shang, Bernhard Vogginger, Yexin Yan, Steve Furber, Christian Mayr
SpiNNaker2 is a scalable neuromorphic chip that combines brain-inspired event-based computing with deep-learning acceleration for more flexible and energy-efficient AI.
Difeng Ma, Changhua Pei, Yuanwei Lu, Quan Zhou, Zexin Wang, Yibo Zhu, Daxin Jiang, Dan Pei, Jingjing Li, Gaogang Xie
Instead of guessing when a GPU will fail, HeaRank identifies which GPUs are most likely to fail so operators can act before problems disrupt large-scale AI jobs.
Siyuan Shen, Anton Korzh, John Bachan, Tiancheng Chen, Arnav Goel, Ludwig Schneider, Pouya Kousha, Zhenhao He, Sylvain Jeaugey, Kamil Iskra, Nishank Chandawala, Jeff R. Hammond, Torsten Hoefler
A new class of ultra-low-latency GPU collectives brings distributed LLM inference and HPC communication within 7% of the hardware speed limit.
Haiyue Ma, Lauren Malek, Joseph Forzani, David Wentzlaff
The paper proposes GPU hardware controls that can dynamically turn down an AI system’s performance as a last-resort safety mechanism.
Shuo Ren, Libo Shen, Yaohui Han, Rongliang Fu, Junying Huang, Bei Yu, Tsung-Yi Ho
Chiplet3D uses a thermally informed MILP to arrange 3D chiplets and pins for shorter connections while substantially reducing hotspots.
Satoshi Matsuoka
This paper argues that rising memory costs and cheaper open models will reshape the AI industry by making inference economics, hardware vintage, and pricing strategy the real battleground from 2026 to 2030.
Bojie Li
OpenURMA is the first open implementation of Huawei’s new Unified Bus protocol, showing that a load/store-style design can cut remote-memory latency and boost throughput versus traditional RDMA.
Kaustav Goswami, Maryam Babaie, Hoa Nguyen, Venkatesh Akella, Jason Lowe-Power
This paper presents CXL-ClusterSim, a new simulation framework for studying how pooled, disaggregated memory over CXL could make large-scale AI and cloud systems more efficient.
Zaid Khan, Justin Chih-Yao Chen, Jaemin Cho, Elias Stengel-Eskin, Mohit Bansal
This paper shows that language models can act like smart GPU performance predictors, helping search systems test more kernel ideas while spending less time on expensive hardware runs.
Giacomo Bernardi, Ratul Mahajan, C. Seshadhri, Enrico Carlesso, Chinchu Merine Joseph, Saurabh Kumar, Pavan Manikonda, Luiza Popa, Randy Ram, Steven Robinson, Elizabeth Tennent
This paper introduces a cheaper, scalable datacenter network design that uses quasi-random graph routing and novel cable-shuffling hardware to beat or match fat-tree performance in production.