AI-Assisted Design of a Post-Quantum Cryptographic Accelerator: A Deployed-Silicon Case Study

This case study describes an agentic AI workflow that took a unified ML-KEM-768 and ML-DSA-65 post-quantum accelerator from Verilog RTL through PCIe bring-up and deployed operation on a Kintex-7 XC7K160T FPGA, including on-chip key custody, shared NTT/INTT and Keccak-f[1600] datapaths, and hardware-generated entropy. Anthropic’s Claude Code, using Claude-family models such as Opus 4.8, worked under human review with Vivado, Python FIPS golden references, and AMD/Xilinx XDMA PCIe infrastructure. The central security finding is that ML-DSA rejection sampling creates message-dependent control paths that fixed known-answer tests cannot fully exercise: a BRAM-latency bug accepted an invalid signature at reject-loop iteration 5 despite passing the complete KAT regression. The replacement validation gate combined byte-exact reference comparison with randomized adversarial soaking, covering 301,343 data-dependent signings within 779,945 checks with zero escapes; the shipped design was also byte-exact across all six FIPS operations. Across 232 logged experiments, the assistant achieved 71.6% task success, with performance declining from 77–85% for documentation and research to 50–53% for synthesis and hardware bring-up, indicating that observability of physical FPGA behavior—not simply task complexity—limited reliability. The final v89 build reached 98.5% slice occupancy and retained 49 ps of setup margin at 500 MHz. End-to-end throughput reached 1,857 ML-KEM encapsulations per second and 480 ML-DSA signatures per second, while OpenSSL integration demonstrated hardware-custodied TLS 1.3 CertificateVerify. The study’s claim is therefore not autonomous hardware authorship, but that artifact-centered validation can establish trust independently of whether RTL was produced by humans or AI.