OpenURMA: A Clean-Room Open Implementation of the Unified Bus Protocol

OpenURMA, from Bojie Li at Pine AI, is the first clean-room open implementation of Huawei’s Unified Bus protocol, developed to address RDMA’s Queue-Pair-over-PCIe bottleneck. Unlike RoCEv2, which maintains per-application, per-remote-endpoint state and requires repeated PCIe crossings, UB separates application endpoints called Jetties from per-host TP Channels, reducing state growth from O(N·M) to O(N+M), places the controller on the CPU’s on-chip bus, and exposes native load/store access with four opt-in ordering axes. The implementation uses a shared OpenClickNP description across synthesizable RTL on an Alveo U50, a cycle-accurate two-node SystemC simulator, and a gem5 full-system scaffold, each compared with matched OpenRoCE. For a 64-byte remote fetch, UB’s load/store path reaches 500 ns end to end versus 2,186 ns for RoCE, a 4.37-fold reduction, while sustaining 2.80-fold higher work-request throughput. At 1,024 local and 1,024 remote endpoints, OpenURMA uses 110.6 KB of connection state versus 536.9 MB for RoCE, a 4,855-fold reduction, and the RTL closes at 322 MHz using 14.1% of the U50’s LUT budget. The study also reports 9.2-fold higher YCSB-A throughput, selective acknowledgments that outperform Go-Back-N under loss, and congestion control reaching 96.0% utilization versus 62.5% for DCQCN. These are modeled and FPGA post-route results rather than measurements on physical UB silicon; Huawei’s Ascend 950 is closed, while NVIDIA’s ConnectX-7 data calibrates the RoCE baseline. The paper states that its code and manuscript were produced with Pine Copilot and Claude Code.